microelectronic
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New microelectronic
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We develop production for the needs of civil microelectronics in accordance with international quality standards
Manufacturer of microelectronic components
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Manufacturer of microelectronic components
NM-TECH is the key of technological development
We carry out testing, measurement, production of MPW
We carry out the supply of technology for the production of microelectronic components for a wide range of civil industries
We cooperate with universities to conduct scientific and technical research in the development and production of products
We provide resources for the development of test chips for the further production of microelectronic components
IC wafer manufacturing innovation center
We carry out verification of IP blocks in silicon
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Services to be provided and planned services
Provision of services for fulfilment of research and development
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Functional control of dies and ICs
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Research of crystals on a wafer
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Fulfillment of orders of design centers and fabless companies
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Development and production of integrated circuits
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Production of microelectronic components on 200 mm silicon wafers
according to customer’s statement of work
for the development and supply of technologies for the production of microelectronic components and test solutions
for identification documents, SIM cards, bank cards, RFID tags and other products together with industrial partners
on 200 mm wafers
in the field of civil microelectronics
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The main potential —
a highly qualified team and advanced equipment
Currently, more than 800 highly qualified specialists of LLC «NM-Tech» implement a project to organize the production and run of production lines for output of microelectronic components to saturate the civil market with a modern electronic component base
The average age of the personnel is 37 years, 11 employees of LLC «NM-Tech» have an academic degree
The main goal of our work is to meet customer needs and create high-quality microelectronics for civilian industry product
The total production area is 43.000 square meters, including 7.500 square meters of cleanrooms according to ISO 6
The Fab has the necessary engineering services that meet international environmental standard
We produce deionized water (100 cmh) and maintain our own cleanroom with a system of anti-vibration platforms for photolithography
Corporate life
Nventing. Improving. Implementing
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    Open vacancies
    As one of the leading companies in the industry, we are delighted to see talented people with different experience in our team.

    If you strive for perfection in your work and are ready to participate in the creation of high technologies that change the world - Join!

    Create your future together with us!

    About the job

    from 130,000 rubles before taxes.
    Required work experience: 5 years and more.
    Full time, full day.
    Responsibilities:
    • Support of digital and analog design flow by means of CAD tools, technical support of their operability.
    • Analysis and evaluation of user cases in the field of design flow.
    • Input control of GDSII, according to factory standards.
    • Approval for the results of input control.

    Requirements:
    Practical development experience in ASIC DOT (RTL to GDS) digital design flow:
    • Confident CAD user of one or more manufacturers (Cadence, Synopsys).
    • Experience with PDK, SC and IO libraries, IP blocks.
    • Experience in logic synthesis of RTL to Netlist and formal verification;
    • Experience in topological synthesis of Netlist to GDS
    • Experience in final layout and GDSII checks;
    • Knowledge of the process of checking projects for design rules (DRC);
    • Technical English.

    The following will be a plus:
    • Developed communication skills.
    • Version storage system user.
    • Familiarity with project management systems (Gnats, Jira, Confluence, Redmine).
    Partial matching in skills and experience is considered.

    Terms:
    • Work in a large manufacturing company.
    • Competitive, officially declared salary.
    • Registration according to the Labor Code of the Russian Federation.
    • Interesting projects, ambitious tasks.
    Technical support engineer
    Send a resume
    About the job
    from 130,000 rubles before taxes.
    Required work experience: 3 years and more.
    Full time, full day.
    Responsibilities:
    • Interaction with associations and consortiums.
    • Participation in the organization of round tables.
    • Assistance in working with universities.
    • Search and coverage of newsworthy information.
    • Copywriting of press releases, articles.
    • Carrying out photo and video recording.
    • Copywriting of advertising texts.
    • Work with site content.

    Requirements:
    • Excellent oral and written communication skills.
    • Confident computer skills.
    • Sociability.
    • Self-discipline and sense of responsibility.
    • Photo and video recording skills.

    Terms:
    • Work in a large manufacturing company;
    • Competitive, officially declared salary;
    • Registration according to the Labor Code of the Russian Federation;
    • Interesting projects, multifaceted tasks.
    Public Relations Manager
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    About the job
    Salary based on the results of the interview
    Required work experience: 3 years and more
    Full time, full day
    Responsibilities:
    • Support and development of software tools for characterization of standard cell libraries, I/O cells, memory blocks and libraries of memory compilers for CMOS technologies.
    • Support and development of software tools for generating behavioral (verilog) and parametric (liberty) representations for library cells and memory blocks.
    • Development and support of tools for forming parametric databases (static and dynamic parameters) of memory compilers.
    • Development and support of software tools for certification of behavioral and parametric representations of library cells and memory blocks.
    • Development of technical documentation.

    Requirements:
    • Higher technical education.
    • Experience in developing programs in C++.
    • Knowledge of scripting programming languages (Shell/Bash, Python/Groovy).
    • Knowledge of Verilog hardware description language.
    • Experience in Cadence CAD is a plus.
    • Knowledge of technical English.

    Terms:
    • Work in a large manufacturing company.
    • Competitive, officially declared salary.
    • Registration according to the Labor Code of the Russian Federation.
    • Interesting projects, ambitious tasks.
    Integrated circuit characterization group software development engineer
    Send a resume
    About the job
    Salary based on the results of the interview.
    Required work experience: 3 years and more.
    Full time, full day.
    Responsibilities:
    • Support and development of the software part of memory compilers - a software package for automated. generation of physical and functional representations of memory blocks for integrated circuits for CMOS technologies.
    • Development and maintenance of programs for support of design flows, memory blocks and libraries of memory compilers, standard cells libraries and I/O cells for CMOS technologies.
    • Development of technical documentation.

    Requirements:
    • Higher technical education.
    • Programming experience in Java8.
    • Strong knowledge of basic JDK libraries.
    • Knowledge of Swing/JavaFX.
    • Knowledge of the gradle/maven build system.
    • Knowledge of scripting programming languages (Python/Groovy).
    • Knowledge of technical English.

    Terms:
    • Work in a large manufacturing company.
    • Competitive, officially declared salary.
    • Registration according to the Labor Code of the Russian Federation.
    • Interesting projects, ambitious tasks.
    Memory Compiler Development Team Software Engineer
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    About the job
    Salary based on the results of the interview.
    Required work experience: 3 years and more.
    Full time, full day.
    Responsibilities:
    • Development of schematic circuit diagrams and maintenance for the development of the layout of logic cell libraries (standard cells (SC), consumption control elements (PMK)) for CMOS technologies.
    • Creation of databases of logic cell representations for the release of libraries.
    • Support and maintenance of standard cell libraries.
    • Development of test blocks for verification of standard cell libraries in silicon.
    • Development of technical documentation.

    Requirements:
    • Higher technical education.
    • Experience in developing schematic diagrams of standard cell libraries for CMOS / SOI technologies.
    • Experience in creating and verifying databases of standard cell libraries (SC libraries).
    • Knowledge of the standard cell library characterization flow.
    • Knowledge of Verilog language at the level of description of library cells.
    • Knowledge of Cadence CAD in terms of analog design flow.
    • Knowledge of technical English.

    Terms:
    • Work in a large manufacturing company.
    • Competitive, officially declared salary.
    • Registration according to the Labor Code of the Russian Federation.
    • Interesting projects, ambitious tasks.
    Memory Compiler Development Team Layout Engineer
    Send a resume
    About the job
    Salary based on the results of the interview.
    Required work experience: 3 years and more.
    Full time, full day.

    Responsibilities:
    • Development of schematic circuit diagrams and maintenance for the development of the layout of logic cell libraries (standard cells (SC), consumption control elements (PMK)) for CMOS technologies.
    • Creation of databases of logic cell representations for the release of libraries.
    • Support and maintenance of standard cell libraries.
    • Development of test blocks for verification of standard cell libraries in silicon.
    • Development of technical documentation.

    Requirements:
    • Higher technical education.
    • Experience in developing schematic diagrams of standard cell libraries for CMOS / SOI technologies.
    • Experience in creating and verifying databases of standard cell libraries (SC libraries).
    • Knowledge of the standard cell library characterization flow.
    • Knowledge of Verilog language at the level of description of library cells.
    • Knowledge of Cadence CAD in terms of analog design flow.
    • Knowledge of technical English.

    Terms:
    • Work in a large manufacturing company.
    • Competitive, officially declared salary.
    • Registration according to the Labor Code of the Russian Federation.
    • Interesting projects, ambitious tasks.
    Standard Cell Libraries Group Layout Engineer
    Send a resume
    About the job
    Salary based on the results of the interview.
    Required work experience: 3 years and more.
    Full time, full day.

    Responsibilities:
    • Development and verification of behavioral models of complex-functional blocks / chips in the Verilog language.
    • Development of constrains for logic synthesis, carrying out the netlist synthesis, verification of synthesized netlist.
    • Development of constrains for the development of the complex-functional blocks/chips layout in the digital design flow.
    • Maintenance of the layout development in the digital design flow, carrying out topological netlist verification.
    • Development of technical documentation.

    Requirements:
    • Higher technical education.
    • Experience in developing and verifying behavioral models of complex-functional blocks / chips in the Verilog language.
    • Experience in developing constrains for netlist logic synthesis, netlist synthesis, verification of the synthesized netlist.
    • Experience in the development of constrains for the development of blocks/chips layout in the digital design flow, verification of the topological netlist.
    • Experience in developing projects using the Low power flow is a plus.
    • Experience in integrating DFT modes into the project is a plus.
    • Knowledge of Cadence CAD in terms of digital design flow.
    • Knowledge of technical English.

    Terms:
    • Work in a large manufacturing company.
    • Competitive, officially declared salary.
    • Registration according to the Labor Code of the Russian Federation.
    • Interesting projects, ambitious tasks.
    Test Chip Development Team Layout Engineer (Digital Circuit Engineer)
    Send a resume
    About the job
    Salary based on the results of the interview.
    Required work experience: 3 years and more.
    Full time, full day.

    Responsibilities:
    • Development of the layout of blocks/chips for CMOS technologies in digital design flow (arrangement of macroblocks, development of a power grid, placement and wiring of standard cells, building a clock tree, temporal static analysis, optimization of the design for timing constraints and consumption parameters).
    • Analysis of the ground/power grid of the project based on IR-drop and electromigration.
    • Carrying out formal verification of the project.
    • Carrying out physical verification of the project.
    • Development of technical documentation.

    Requirements:
    • Higher technical education.
    • Experience in developing the layout of blocks/chips for CMOS technologies in a digital design flow using Cadence CAD (floorplan, place&route, STA, timing&power signoff analyses).
    • Experience in carrying out formal verification of the project.
    • Experience with physical verification tools of layout (DRC/LVS).
    • Knowledge of scripting programming languages.
    • Knowledge of Low Power and DFT flow is a plus.
    • Knowledge of technical English.

    Terms:
    • Work in a large manufacturing company.
    • Competitive, officially declared salary.
    • Registration according to the Labor Code of the Russian Federation.
    • Interesting projects, ambitious tasks.
    Layout Development Group Design Engineer (Digital Layouter)
    Send a resume
    Public Relations Manager
    MORE
    14.02.2023
    - Interaction with associations
    - Writing of articles, press releases
    - Carrying out photo and video recording
    Technical support group specialist
    - support of digital and analog design flow by means of CAD tools, technical support of their operability
    - input control of GDSII, according to factory standards
    MORE
    14.02.2023
    Developer for electrostatic discharge protection devices and circuits
    - Developing ESD protection circuits for products with different levels of protection and requirements.
    - Work with several product lines in parallel, interaction with design.
    MORE
    27.03.2023
    15.02.2023
    Memory Compiler Development Team Layout Engineer
    - Development of schematic circuit diagrams of memory compiler libraries.
    - Development of schematic circuit diagrams of memory blocks/memory chips.
    MORE
    Memory Compiler Development Team Software Engineer
    - Development of the software part of memory compilers.
    - Development of programs for support of design flows, libraries of memory compilers for CMOS technologies.
    MORE
    15.02.2023
    Integrated circuit characterization group software development engineer
    - Development of software tools for characterization of standard cell libraries
    - Development of software tools for generating behavioral (verilog)
    MORE
    15.02.2023
    Смотреть еще
    15.02.2023
    Layout Development Group Design Engineer
    - Development of the layout of blocks/chips for CMOS technologies in digital design flow.
    - Carrying out formal and physical verification of projects.
    MORE
    Test Chip Development Team Layout Engineer
    - Development and verification of behavioral models of complex-functional blocks / chips in the Verilog language.
    - Carrying out the netlist logic synthesis and maintenance for the development of the layout in the digital design flow.
    MORE
    15.02.2023
    Standard Cell Libraries Group Layout Engineer
    - Development of schematic diagrams of logic cell libraries.
    - Creation and maintenance of databases of logic cell libraries representations.
    MORE
    15.02.2023
    About the job
    Salary based on the results of the interview.
    Required work experience: 3 years and more.
    Full time, full day.

    • Development of ESD devices with different degrees of protection and frequency response characteristics;
    • Preparation and maintenance of test structures in test chips and MPW;
    • Development of ESD event protection circuits according to specified requirements;
    • Creation of electrical circuits in the Virtuoso Schematic environment;
    • Development of testbenches for subsequent simulation with Spice simulator in Virtuoso ADE Explorer environment;
    • Creation of technical documentation for ESD protection circuits;
    • Preparation of technical documentation for measuring works;
    • Interaction with the team for the development of cells of interface elements;
    • Working with product line design departments
    Developer for electrostatic discharge protection devices and circuits
    Send a resume
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        +7 (499) 995 00 70
        info@nm-tech.org
        Moscow, Zelenograd, Solnechnaya Alley, 6, floor 1, Room XII, office 4, 4A
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